
4-3 Interface block diagram LD-16712C-7
8Bi
Mode
LVDS_SET=L (20 pin=GND or OPEN)
8Bi
Mode
LVDS_SET=H (20 pin=3.3[V])
6Bi
Mode
LVDS_SET=H (20 pin=3.3[V])
(Computer Side)
(TFT-LCD side)
TC 0 - 6
TA 0 - 6
TB 0 - 6
R0-R5,G0
B2-B5, NA,NA,DE
G1-G5,B0,B1
RX0+(6)
RX0-(5)
TD 0 - 6
7
Controll
TTL PARALLEL-TO-LVDS
PLL
THC63LVDM83
PLL
RX1+(9)
RX1-(8)
RX2+(12)
RX2-(11)
CK+(15)
CK-(14)
CK
CLK IN
Single LVDS interface contained in a control
RX3+(18)
RX3-(17)
7
7
7
R6,R7,G6,G7,
B6,B7,NA
Internal circuits
RC 0 - 6
RA 0 - 6
RB 0 - 6
RD 0 - 6
CK OUT
LVDS-TO-PARALLEL TTL
TC 0 - 6
TA 0 - 6
TB 0 - 6
R2-R7,G2
B4-B7, NA,NA,DE
G3-G7,B2,B3
RX0+(6)
RX0-(5)
TD 0 - 6
7
Controll
TTL PARALLEL-TO-LVDS
PLL
THC63LVDM83
PLL
RX1+(9)
RX1-(8)
RX2+(12)
RX2-(11)
CK+(15)
CK-(14)
C
CLK IN
Single LVDS interface contained in a control IC
RX3+(18)
RX3-(17)
7
7
7
R0,R1,G0,G1,
B0,B1,NA
Internal circuits
RC 0 - 6
RA 0 - 6
RB 0 - 6
RD 0 - 6
CK OUT
LVDS-TO-PARALLEL TTL
TC 0 - 6
TA 0 - 6
TB 0 - 6
R0-R5,G0
B2-B5, NA,NA,DE
G1-G5,B0,B1
RX0+(6)
RX0-(5)
TD 0 - 6
7
Controll
TTL PARALLEL-TO-LVDS
PLL
THC63LVDM83
PLL
RX1+(9)
RX1-(8)
RX2+(12)
RX2-(11)
CK+(15)
CK-(14)
C
CLK IN
Single LVDS interface contained in a control IC
RX3+(18)
RX3-(17)
7
7
7
GND×6,NA
Internal circuits
RC 0 - 6
RA 0 - 6
RB 0 - 6
RD 0 - 6
CK OUT
LVDS-TO-PARALLEL TTL
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